In a digital memory system, a memory controller 10 may control operations of a memory module 20 including a plurality of memory devices 30 separately identified as M1-M9. More particularly, each memory device 30 may be an integrated circuit dynamic random access memory device.
Data signals DATA1-DATA9 can be transmitted between the memory controller 10 and the separate memory devices 30 using separate data signal bus lines. During a read operation, data signals DATA1-DATA9 can be read from the memory devices M1-M9 to the memory controller 10 over the separate data bus lines at the same time, and during a write operation, data signals DATA1-DATA9 can be written from the memory controller to the memory devices M1-M9 at the same time. In addition, separate lines for data strobe signals DQS1-DQS9 and separate lines for data mask signals DM1-DM9 are provided between memory controller 10 and each of the memory devices M1-M9. Accordingly, a propagation delay between the memory controller 10 and each of the memory devices M1-M9 may be approximately the same for data signals DATA1-DATA9, data strobe signals DQS1-DQS9, and data mask signals DM1-DM9. The arrangement of FIG. 1 with separate data buses between the memory controller 10 and each of the memory devices M1-M8 may be referred to as providing point-to-point connections.
In contrast, a same control/address/clock bus 12 may couple control/address signals CA and a system clock signal CK from the memory controller 10 to each of the memory devices M1-M9. Accordingly, a length of the transmission line for the clock signal CK may be different for each of the memory devices M1-M9 so that a propagation delay of the clock signal CK may vary for each of the memory devices M1-M9. If the memory devices M1-M9 are evenly spaced along the control/address/clock bus 12, the clock signal CK may experience an incremental propagation delay T (also referred to as a phase difference or phase shift) for each memory device M1-M9 in the module. Arbitrarily assigning a propagation delay of 0 for the first memory device M1, for example, the clock signal CK propagation delay of T may result at second memory device M2, a propagation delay of 2T may result at third memory device M3, a propagation delay of 3T may result at fourth memory device M4, a propagation delay of 4T may result at fifth memory device M5, a propagation delay of 5T may result at sixth memory device M6, a propagation delay of 6T may result at seventh memory device M7, a propagation delay of 7T may result at eighth memory device M8, and a propagation delay of 8T may result at ninth memory device M9. The arrangement of FIG. 1 with the clock signal CK being provided to each of the memory devices M1-M9 is referred to as providing a fly-by clock.
Reading and writing data signals DATA1-DATA9 provided over respective point-to-point data buses may be synchronized with the fly-by system clock signal CK provided to each of the memory devices over a same system clock signal line. At relatively high operating speeds, however, it may be difficult to synchronize transfers of data signals DATA1-DATA9 over the respective point-to-point data buses where the system clock signal CK is provided to the different memory devices M1-M9 with different propagation delays.
FIG. 2 illustrates the memory module 20 including nine memory devices 30 separately identified as M1-M9. As shown, each memory device 30 includes eight data pins PDQ1-PDQ8, a data mask pin PDM, and a data strobe pin PDQS separately connected to the memory controller. As shown, data signals DQ1-8 (i.e. DATA1) are provided to/from data pins PDQ1-PDQ8 of memory device M1; data signals DQ9-DQ16 (i.e. DATA2) are provided to/from data pins PDQ1-PDQ8 of memory device M2; data signals DQ17-DQ24 (i.e. DATA3) are provided to/from data pins PDQ1-PDQ8 of memory device M3; data signals DQ25-DQ32 (i.e. DATA4) are provided to/from data pins PDQ1-PDQ8 of memory device M4; data signals DQ33-DQ40 (i.e. DATA5) are provided to/from data pins PDQ1-PDQ8 of memory device M8; data signals DQ41-DQ48 (i.e. DATA6) are provided to/from data pins PDQ1-PDQ8 of memory device M6; data signals DQ49-DQ56 (i.e. DATA7) are provided to/from data pins PDQ1-PDQ8 of memory device M7; data signals DQ57-DQ64 (i.e. DATA8) are provided to/from data pins PDQ1-PDQ8 of memory device M8; and data signals DQ65-DQ726 (i.e. DATA2) are provided to/from data pins PDQ1-PDQ8 of memory device M9. Data mask signals DM1-DM9 are provided to respective data mask pins PDM of each memory device M1-M9 through separate data mask lines, and data strobe signals DQS1-DQS9 are provided to respective data strobe pins PDQS of each memory device M1-M9 through separate data strobe lines.
As used herein, the term pin is defined to include any input or output structure of an integrated circuit memory device providing electrical connectivity to another device, substrate, and/or circuit board. For example, the term pin may include: leads of a dual in-line package (DIP), a single in-line package (SIP), a pin grid array (PGA), quad small outline package (QSOP), etc.; solder bumps of a flip-chip, ball grid array, etc.; wire bonds; bonding pads; etc.
Moreover, each memory device M1-M9 includes a plurality of clock/command/address pins PCA coupled to a same clock/command/address bus 12. The system clock signal CK and the command/address signals CA are provided to the clock/command/address pins of memory devices M1-M9 over the clock/command/address bus 12. The address signals transmitted over the clock/command/address bus 12 define memory locations of the memory devices M1-M9 to which or from which data signals DATA1-DATA9 should be written or read. More particularly, the address signals may define bank addresses and row/column addresses. A memory device, for example, may include four banks of memory cells, and each memory bank may operate with selected row and column addresses independently.
The command signals transmitted over the clock/command/address bus 12 define operations to be performed by the memory devices M1-M9. Command signals may define commands such as a row active command (ACTIVE), a read command (READ), a write command (WRITE), a refresh command (PEF), a power down command (PWDN), a mode register set command (MRS), etc. Command pins may include a clock enable pin, a chip select pin, a row address strobe pin, a column address strobe pin, and a write enable pin. FIG. 3A is a diagram illustrating pins of a integrated circuit dynamic random access memory device, and FIG. 3B is a table describing pin functionalities of the memory device of FIG. 3A.
FIG. 4 is a block diagram illustrating functional blocks of a memory device. As shown, the memory device 30 includes command decoder 34, address buffer 35, internal clock generator 36, data I/O buffer 37, row decoder 32, column decoder 33, memory cell array 31, and sense amplifier 38. As shown, command signals CMD of the clock/command/address signals CA are provided to the command decoder 34, address signals ADD of the clock/command/address signals CA are provided to the address buffer 35, and the system clock signal CK of the clock/command/address signals CA is provided to the internal clock generator 36. The internal clock generator 36 generates an internal clock signal iCLK responsive to the system clock signal CK.
Accordingly, the command decoder 34 decodes the command signals CMD to determine a particular operation (such as a read operation, a write operation, or a mode register set operation) to be performed. During a mode register set operation, a value is written to a mode register to define a mode of operation for the memory device. During a write operation, data signals DATA from the memory controller are received at the data I/O buffer 37 and written as iDATA to locations of the memory cell array 31 defined by address signals ADD received from the memory controller. During a read operation, iDATA from locations of the memory cell array defined by address signals ADD received from the memory controller is retrieved by the data I/O buffer 37 and provided as data signals DATA to the memory controller. As shown in FIG. 4, the data I/O buffer 37 operates responsive to the iCLK signal generated by the internal clock generator 36.
FIG. 5 is a timing diagram illustrating a read operation of the memory module 20 including a plurality of memory devices 30, where the read operation is initiated responsive to a read command READ received over the clock/command/address data bus 12. Due to different propagation delays along the clock/command/address bus 12, the system clock signal CK may be shifted in phase at each of the memory devices M1-M9. In FIG. 5, signal CK1 is the system clock signal CK as received at memory device M1, signal CK5 is the system clock signal CK as received at memory device M5, and signal CK9 is the system clock signal CK as received at memory device M9. The internal clock signal iCLK5 of memory device M5 is thus delayed by an interval of 4T relative to the internal clock signal iCLK1 of memory device M1, and the internal clock signal iCLK9 of memory device M9 is delayed by an interval of 4T relative to the internal clock signal iCLK5 of memory device M5. Because the internal clock signals are not synchronized and because the data I/O buffers of the memory devices operate responsive to the respective internal clock signals, the data signals DATA1-DATA9 will be provided out of the respective memory devices at different times resulting in data skew. As shown in FIG. 5, the data signals DATA9 out of the memory device M9 are thus delayed by an interval 4T relative to the data signals DATA5 out of the memory device M5, and the data signals DATA5 out of memory device M5 are delayed by an interval 4T relative to the data signals DATA1 out of memory device M1. The data skew may limit an operating speed of the memory module during a write operation.
FIG. 6 is a timing diagram illustrating a write operation of the memory module 20 including a plurality of memory devices 30, where the write operation is initiated responsive to a write command WRITE received over the clock/command/address data bus 12. Due to different propagation delays along the clock/command/address bus 12, the system clock signal CK may be shifted in phase at each of the memory devices M1-M9. In FIG. 6, signal CK1 is the system clock signal CK as received at memory device M1, signal CK5 is the system clock signal CK as received at memory device M5, and signal CK9 is the system clock signal CK as received at memory device M9. The internal clock signal iCLK5 of memory device M5 is thus delayed by an interval of 4T relative to the internal clock signal iCLK1 of memory device M1, and the internal clock signal iCLK9 of memory device M9 is delayed by an interval of 4T relative to the internal clock signal iCLK5 of memory device M5. Because the internal clock signals are not synchronized and because the data I/O buffers of the memory devices operate responsive to the respective internal clock signals, the external data signals DATA1-DATA9 will be provided by the memory controller at the same time, but the internal data signals iDATA1-iDATA9 will be generated by the respective data input/output buffers at different times resulting in data skew. As shown in FIG. 6, the internal data signals iDATA9 for the memory device M9 are thus delayed by an interval 4T relative to the internal data signals iDATA5 for the memory device M5, and the internal data signals iDATA5 for the memory device M5 are delayed by an interval 4T relative to the internal data signals iDATA1 for memory device M1. The data skew may limit an operating speed of the memory module during a write operation.